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Ability to independently develop FPGA and FPGA platform requirements specifications.Experience in coding and debugging Verilog.Experience with FPGA synthesis, placement and timing closure.Experience with USB 3, MIPI and Ten-Silica is a plusExperience in system timing analysis.Equivalent experience in ASIC design will also receive consideration.Strong lab troubleshooting skills.
Posted - 02/07/15
RF System and Board design Engineer
You must have a BSEE or MSEE with at least 5+ years experience in developing products based on RF subsystems. Prefer design experience in 60GHz RF design. Responsibilites include board design and debug.
Develop Dual site ATE solution from a working single site solution for the TMT ASL1000 based tester. Position in Santa Clara, CA
Principal Physical Design Engineer
Ownership of design floor planning, synthesis, DFT, place and route, clock and power distribution, static timing analysis, signal integrity analysis, physical verification. Experience with Cadence tools required. Position in Santa Clara, CA